• PUBLICATIONS

    论文与研究成果

    姓名后的 * 表示通讯作者。

    2026

    1. Ying Liu, Chan Shan, Tin Tin Ting*, TCAD-based evaluations of a PNPN tunneling field effect transistor based on GaAs cladding layer, Micro and Nanostructures 2026, 209: 208395. (SCI，JCR二区)

      GaAs 包覆层 PNPN 隧穿场效应晶体管结构，以及载流子浓度和带间隧穿率分析图
      GaAs 包覆层 PNPN-TFET 的器件结构，以及载流子浓度与带间隧穿（BTBT）分布、截线分析结果。
      查看研究简介研究目的、方法、结果与意义

      本研究围绕低功耗隧穿器件的性能与制造可行性，提出了一种具有良好尺寸扩展能力的 GaAs 包覆层 PNPN-TFET。

      研究目的
      设计一种能够形成 PNPN 隧穿结、又可减少窄区域复杂外延或离子注入步骤的新型 TFET，为后续器件缩放与低功耗集成提供更可实现的结构方案。
      器件设计与方法
      利用电荷等离子体效应和 GaAs 包覆层，在源区诱导形成 P+ 载流子分布；结合给出的器件制备流程与校准后的 TCAD 数值模型，系统分析载流子浓度、带间隧穿率、结构参数、直流开关特性及模拟/射频性能。
      关键结果
      器件获得 26.1 μA/μm 的开态电流和 3.73 × 10¹² 的开关电流比；在 0.7 V 偏压下，峰值截止频率达到 73.76 GHz，体现出较好的开关能力与高频潜力。
      研究意义
      GaAs 包覆层与电荷等离子体机制协同增强源—沟道隧穿，同时降低传统 PNPN 结构中局部重掺杂工艺的实现难度，为可扩展、低功耗的隧穿晶体管设计提供了新思路。
      • 26.1 μA/μm开态电流
      • 3.73 × 10¹²开关电流比
      • 73.76 GHz峰值截止频率
      • 0.7 V测试偏压

    2. Chan Shan, Qian-nan Wang, Ying Liu*, Performance Analysis of An In-built N+ Pocket Electrically Doped TFET Biosensor for Biomedical Applications, Chinese Physics B 2026, 35(2): 028703. (SCI，JCR三区)

      内建 N+ 口袋电掺杂 TFET 生物传感器结构与不同生物分子灵敏度对比图
      内建 N+ 口袋 ED-TFET 生物传感器的纳米腔结构，以及代表性生物分子的漏电流灵敏度对比。
      查看研究简介研究目的、方法、结果与意义

      本研究将内建 N+ 口袋电掺杂 TFET 与纳米间隙腔体结合，用于评估面向生物医学检测的高灵敏度器件方案。

      研究目的
      在简化局部掺杂工艺的同时，提高 TFET 对生物分子介电性质与电荷状态的响应能力，探索适用于低功耗生物医学检测的器件结构。
      器件设计与方法
      器件通过极性栅偏置形成内建 N+ 口袋区，避免额外掺杂步骤；在靠近源端的栅介质区域设置纳米间隙腔体。研究分别考察中性和带电生物分子，并分析漏电流、能带、电场、亚阈值摆幅、阈值电压与开关电流比的变化。
      关键结果
      当介电常数 k = 12 的中性生物分子完全填充纳米腔时，器件获得 1.08 × 10¹³ 的峰值灵敏度；研究同时揭示了腔体几何参数与填充因子对传感响应的影响。
      研究意义
      该方案以电掺杂方式构建关键载流子区域，并把纳米腔介电调制直接转化为电学响应，为高灵敏度、低功耗 TFET 生物传感器的结构优化提供了依据。
      • 1.08 × 10¹³峰值灵敏度
      • k = 12对应介电常数
      • N+ Pocket内建口袋结构
      • Nanogap纳米腔检测区域

    3. Chan Shan, Ying Liu*, Simulation And Design of Asymmetric Vertical Cladding Layer-Based Tunneling Field Effect Transistors With Improved DC and Analog/RF Performance, Microelectronics Journal 2026, 172: 107145. (SCI，JCR三区)

      传统垂直包覆层 TFET 与非对称垂直包覆层 TFET 结构、隧穿率和电场分布对比图
      VCL-TFET 与 AVCL-TFET 的器件结构对比，以及非局域带间隧穿率和电场分布。
      查看研究简介研究目的、方法、结果与意义

      本研究提出带有延伸源区的非对称垂直包覆层 TFET（AVCL-TFET），重点改善器件的直流、模拟与射频综合性能。

      研究目的
      针对常规 TFET 开态电流与高频性能受限的问题，通过非对称包覆层和源区工程增强源—沟道隧穿，兼顾低功耗开关与模拟/RF 应用需求。
      器件设计与方法
      在垂直包覆层结构中引入延伸源区，使源—沟道界面的线隧穿与点隧穿共同增强；包覆层在本征锗源区诱导空穴层，无需额外感应金属。研究给出可扩展的制备流程，并采用二维 TCAD 对结构、电场、非局域带间隧穿率及小信号指标进行评估。
      关键结果
      AVCL-TFET 实现 110 μA/μm 的开态电流、2.92 × 10¹⁰ 的开关电流比、394 μS/μm 的峰值跨导，以及 51.18 GHz 的最大截止频率。
      研究意义
      结果表明，非对称包覆层与延伸源区能够有效重塑电场和隧穿路径，为兼顾直流驱动能力与高频响应的低功耗 TFET 提供了可行的结构优化方向。
      • 110 μA/μm开态电流
      • 2.92 × 10¹⁰开关电流比
      • 394 μS/μm峰值跨导
      • 51.18 GHz最大截止频率

    4. Qian-nan Wang, Ying Liu, Tin Tin Ting and Chan Shan*, Design and Performance of A Dielectrically Modulated PNPN TFET Biosensor Based on GaAs Cladding Layer, Physica Scripta 2026, 101(31): 315005. (SCI，JCR二区)

    5. Yi-Jiao Lin, Ying Liu, Tin Tin Ting and Chan Shan*, Design and Simulation of Reduced Ambipolar Effect for PNPN Tunnel FETs Using Dual Cladding Layers, Physica Status Solidi (A)-Applications and Materials Science 2026, 223(1): e202500862. (SCI，JCR三区)

    6. Yu Han, Ying Liu, Tin Tin Ting, Yu-chen Wang, Yuan Long and Chan Shan*, Improvement of Extended-Source TFET with Dopant-segregated Schottky-barrier Drain for Ambipolar Performance, Physica Status Solidi (A)-Applications and Materials Science 2026, 223(2): e202500688. (SCI，JCR三区)

    7. Wen-Bin Xu, Ying Liu*, Tin Tin Ting, Drain Work Function Engineered Electrically Doped PNPN TFET for Ambipolar Suppression, Semiconductors 2026, 60(4): 431-442. (SCI，JCR四区)

    2025

    1. Hang-Huang Zhang and Chan Shan*, In-Built N+ Pocket Dual-Material Gate Electrical-Doped Tunnel Field-Effect Transistors with Dopant-Segregated Schottky Barrier Drain for Ambipolarity Suppression, Physica Status Solidi (A)-Applications and Materials Science 2025, 222(16): 2500267. (SCI，JCR三区)

    2. Qian-nan Wang, Ying Liu*, Chan Shan, High-Sensitivity In-Built N+ Pocket Electrically Doped Tunnel FET Biosensor with Nanogap Cavity, 2025 8th International Conference on Advanced Electronic Materials, Computers and Software Engineering (AEMCSE), 59-62. (IEEE会议论文，EI检索)

    2023

    1. Chan Shan, Ying Liu*, Yuan Wang, Rongsheng Cai and Lehui Su, Electrically Doped PNPN Tunnel Field-Effect Transistor Using Dual-Material Polarity Gate with Improved DC and Analog/RF Performance, Micromachines 2023, 14(12): 2149. (SCI，JCR二区)

    2. Chan Shan, Lan Yang, Ying Liu*, Zi-Meng Liu, Han Zheng, Controlling Drain Side Tunneling Barrier Width in Electrically Doped PNPN Tunnel FET, Micromachines 2023, 14(2): 301. (SCI，JCR二区)

    3. Ying Liu, Yuan Wang, Chan Shan, Lian-Ying Ou-Yang, Shu-Rong Wang, Ping-Ting Ruan, Ge-Jing Xu*, Sub-10-nm Tunnel Field-Effect Transistor with Schottky Drain, 2023 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS). (IEEE会议论文，EI检索)

    2022

    1. Chan Shan, Ying Liu*, Huan Chen, Dong-yang Huo, Tian-rong Xu, An n-MOSFET Layout with Multi-Finger Z Gate for Radiation Tolerance, 2022 IEEE 5th International Conference on Knowledge Innovation and Invention (ICKII), 42-44. (IEEE会议论文，EI检索)

    2. Yi Liu, Sufen Wei, Chan Shan, Mingjie Zhao, Shui-Yang Lien, Ming-kwei Lee, Compositions and properties of high-conductivity nitrogen-doped p-type β-Ga2O3 films prepared by the thermal oxidation of GaN in N2O ambient, Journal of Materials Research and Technology 2022, 21: 3113-3128. (SCI，JCR一区)

    2020

    1. Jun Li, Ying Liu, Su-fen Wei, Chan Shan*, In-Built N+ Pocket Electrically Doped Tunnel FET With Improved DC and Analog/RF Performance, Micromachines 2020, 11(11): 960. (SCI，JCR二区)

    2018

    1. Ying Wang*, Chan Shan, Wei Piao, Xing-ji Li, Jian-qun Yang, Fei Cao and Cheng-hao Yu, 3-D Numerical Simulation of Z Gate Layout MOSFET for Radiation Tolerance, Micromachines 2018, 9(12): 659. (SCI，JCR二区)

    2. Fei Cao, Chan Shan, Ying Wang*, Xin Luo, Cheng-hao Yu, SOI-like MOSFET with ESD and self-heating effect reliability improvements, Micro & Nano Letters 2018, 13(12): 1649-1652. (SCI，JCR三区)

    3. Lijie Li, Chan Shan, Ying Wang*, Xin Luo, Negative bias temperature instability in SOI-like p-type metal oxide semiconductor devices, Micro & Nano Letters 2018, 13(8): 1151-1154. (SCI，JCR三区)

    2017

    1. Chan Shan, Ying Wang*, Xin Luo, Meng-tian Bao, Cheng-hao Yu, Fei Cao, A High-Performance Channel Engineered Charge-Plasma-Based MOSFET With High-κ Spacer, Superlattices and Microstructures 2017, 112: 499-506. (SCI，JCR二区)

    2. Yan-Juan Liu, Ying Wang*, Yue Hao, Jun-Peng Fang, Chan Shan, Fei Cao, A Low Turn-Off Loss 4H-SiC Trench IGBT With Schottky Contact in the Collector Side, IEEE Transactions on Electron Devices 2017, 64(11): 4575-4580. (SCI，JCR一区)

    3. Ying Wang*, Chan Shan, Chao-ming Liu, Xing-ji Li, Jian-qun Yang, Yan Tang, Meng-tian Bao and Fei Cao, Graded-channel Junctionless Dual-gate MOSFETs for Radiation Tolerance, Japanese Journal of Applied Physics 2017, 56(12): 124201. (SCI，JCR三区)

    2016

    1. Chan Shan, Ying Wang* and Meng-tian Bao, A Charge-Plasma Based Transistor with Induced Graded Channel for Enhanced Analog Performance, IEEE Transactions on Electron Devices 2016, 63(6): 2275-2281. (SCI，JCR一区)

    2015

    1. Ying Wang*, Chan Shan, Zheng Dou, Li-guo Wang, Fei Cao, Improved Performance of Nanoscale Junctionless Transistor Based on Gate Engineering Approach, Microelectronics Reliability 2015, 55(2): 318-325. (SCI，JCR二区)

    2. Ying Wang*, Xiao-Wen He, Chan Shan, A Simulation Study of Hot Carrier Effects in SOI-Like Bulk Silicon nMOS Device, IEEE Transactions on Electron Devices 2015, 62(1): 23-27. (SCI，JCR一区)

    2014

    1. Ying Wang*, Xiao-Wen He, Chan Shan, A Simulation Study of SOI-Like Bulk Silicon MOSFET With Improved Performance, IEEE Transactions on Electron Devices 2014, 61(9): 3339-3344. (SCI，JCR一区)

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